During the process of making semiconductor devices, capacitors are formed by the application of various steps to selected areas that are to include capacitors. Capacitors can be formed during the front-end-of-the-line (FEOL) processes used to make semiconductor devices. These capacitors have drawbacks, however, such as high resistance and unwanted parasitic capacitance which degrade the tunability (Q) of the capacitor. Capacitors can also be formed during the back-end-of-the-line (BEOL) wiring processes used to make semiconductor devices. These capacitors also have drawbacks, namely the poor quality of deposited insulators on metal resulting in low per unit area capacitance.
Trench capacitors have been developed as a way to achieve cells with larger capacitance values without increasing the area these cells occupy on the chip surface. For example, the silicon area reduction of a trench capacitor compared to a planar capacitor for the same specific capacitance is a factor of 18 or more. Although many of the processing details involved in trench capacitor fabrication are the same as the processing technology of trench isolation structures, there are some unique differences.
There are several differences between the trench structures used for isolation and those used as capacitors. In the former, the dielectric film on the trench walls may be relatively thick, and the trench may be refilled with polysilicon or chemical vapor deposition (CVD) SiO2. In the latter, the insulator formed on the trench walls may serve as the capacitor dielectric and, therefore, it must be as thin as possible. Because the material that refills the trench serves as one plate of the capacitor, it typically consists of highly doped polysilicon. Furthermore, in order to obtain increased capacitance through increases in trench depth, while all other parameters remain constant, the trench walls must be highly vertical. Some trench sidewall slope is usually needed, however, to allow for reliable refilling of the trenches.
Techniques have been tried for achieving a dielectric capacitor film that is thin enough to provide both high capacitance and high reliability. That is, the dielectric must be able to provide the same equivalent breakdown voltage as the planar capacitor. Such composite dielectric films as thermally grown oxide and CVD nitride may be used; thermal oxide films may also present problems. Unless preventative measures are taken, a thinner oxide may grow in the bottom corners and the top corners of the trench. Consequently, a higher electric field may exist across these regions, causing trench capacitors to exhibit higher leakage currents than planar capacitors.
U.S. Pat. No. 5,658,821 issued to Chen et al. describes a process for the formation of capacitors having a polysilicon first capacitor plate, an oxide dielectric, and a metal second capacitor plate which improves uniformity of capacitance and avoids device damage. The process described, however, requires preconditioning of the surface of the polysilicon first capacitor plate to achieve uniform and well-controlled polysilicon oxide formation. The preconditioning requires the additional steps of forming a thin first oxide layer on the polysilicon first capacitor plate. This step is followed by an oxide etch and a dry vertical anisotropic etch. The thin layer of polysilicon oxide is then removed from the polysilicon first capacitor plate, thus conditioning the polysilicon so that subsequent oxide formations may be uniform and well controlled.
The deficiencies of the conventional processes used to make capacitors which are uniform and reliable show that a need still exists for a process which can make uniform and reliable capacitors. Moreover, a need still exists to make high-Q capacitors which do have neither high resistances nor unwanted parasitic capacitance. Furthermore, a need exists to make high-Q capacitors which may be densely formed and have a high per unit area capacitance.